NXP上海 招聘数字IC设计工程师
浏览量:769 回帖数:0
1楼
工作地点:上海市
招聘性质:社招
工作描述:
Job description
About the Position:
As a member of a Shanghai wireless Design For Test(DFT) team, the candidate will work with DFT Lead(US base) and SOC team to design, develop BSCAN, MBIST and perform scan/edt insertion as well as pattern generation for various mixed-signals Chips.
The member will also need design customized DFT module and develop the verification plan for DFT modules.
Responsibilities:
* Tessent MBIST flow implementation/automation
* Scan/EDT insertion and ATPG with Mentor tools. Verification of DFT Logic and analysis of fault coverage
* Timing analysis for DFT Modes
* ATE pattern delivery and bring-up
* Travelling for ATE bring-up(to US/Taiwan site) may be needed but not mandatory
Minimum Qualifications:
* Candidate MUST be MS degree or above in CS/EE or related technical field(s)
* Knowledge of Logic design & Static timing analysis
* Knowledge of Verilog, SV and any scripting language(perl, etc)
Preferred Qualifications:
* 3+ years (including internships) excellent Design Development and ATE debug experience in MBIST, SCAN/ATPG with Tessent flow
* Good verbal and written communication skills in English
* Good design automation skills(Perl scripting etc)
有意向者可发送简历至:pingying.zeng@nxp.com
招聘性质:社招
工作描述:
Job description
About the Position:
As a member of a Shanghai wireless Design For Test(DFT) team, the candidate will work with DFT Lead(US base) and SOC team to design, develop BSCAN, MBIST and perform scan/edt insertion as well as pattern generation for various mixed-signals Chips.
The member will also need design customized DFT module and develop the verification plan for DFT modules.
Responsibilities:
* Tessent MBIST flow implementation/automation
* Scan/EDT insertion and ATPG with Mentor tools. Verification of DFT Logic and analysis of fault coverage
* Timing analysis for DFT Modes
* ATE pattern delivery and bring-up
* Travelling for ATE bring-up(to US/Taiwan site) may be needed but not mandatory
Minimum Qualifications:
* Candidate MUST be MS degree or above in CS/EE or related technical field(s)
* Knowledge of Logic design & Static timing analysis
* Knowledge of Verilog, SV and any scripting language(perl, etc)
Preferred Qualifications:
* 3+ years (including internships) excellent Design Development and ATE debug experience in MBIST, SCAN/ATPG with Tessent flow
* Good verbal and written communication skills in English
* Good design automation skills(Perl scripting etc)
有意向者可发送简历至:pingying.zeng@nxp.com
2021/8/14 1:39:44