10K-20K 上海 应届毕业生 硕士及以上 全职
职位□□: 顶尖技术
Design Engineer
• position description
Candidates will be involved in the whole ASIC design flow from RTL coding through P&R support, which includes logic design, DFT planning and implementation, logic synthesis, power optimization, static timing analysis and sign-off. Candidates will also work closely with analog design teams on IP integration, with P&R engineers on chip floor planning and timing optimization, and with product/test engineers on ATE tests.
• Job Description
Work closely with frontend and backend design teams, as well as test engineers.　Participate in logic design for some timing critical blocks in SOHO switch/PHY chips and ASICs.　Perform logic synthesis, floor planning, timing analysis and timing signoff for chip tapeout. Work on DFT designs including MBIST, EDT, OCC, JTAG. Run Mentor and Synopsys tools to create and verify ATPG patterns. Work with test engineers to build up and debug test programs.
• Job qualification
• MSEE degree
• 0~2 years of hand-on experience in digital design, running EDA tools of simulation,　　 synthesis, timing analysis and formal verification
• Solid knowledge and background in ASIC development
　Good communication skills

详情请扫描下方二维码：